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I/O Modules

ARM Core Tile ARM-7TDMI, ARM926EJ-S, ARM1136JF-S
DDR3 SO-DIMM, DDR2 SO-DIMM
32MB NorFLASH, 64MB SDRAM
128MB DDR SDRAM, UART/USB2.0
Gigabit Ethernet Phy, PCI Express Phy
DVI, HDMI, TFT LCD, CMOS Image Sensor
Debugging&Proving
ARM Core or DSP Interface

<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' style="VERTICAL-ALIGN: middle; CURSOR: pointer" onclick=image_window(this) name=target_resize_image[] src="/_data/_editor/1003/2040968486_161da8fd_square_arrow.gif" tmp_width="14" tmp_height="16" > 제품 개요 
RPS-LX7601, RPS-LX7604는 SoC 설계를 위한 검증 FPGA보드로서 ARM Core 및 주변 회로를 검증합니다. 검증시 다양한CPU 및 주변장치가 필요로하게 됩니다. 사용자가 원하는 Peripherals Module 들을 다양하게 제공하는 경우 사용자는 빠른 시간내에 개발을 할 수 있습니다. 이미 검증된 I/O Module을 사용하여 H.264, MPEG, CIS, AMBA Bus, DVI, Ethernet, PCI Express 등의 회로를 구현할 수 있습니다. 또한 사용자가 원하는 모듈을 설계제공함으로써 사용자가 로직의 개발능력을 충분히 발휘할 수 있도록 하고 있습니다.  1.     ARM Core Tile & 삼성 ARM11, Cortex A8 Core 
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Item <o:p></o:p></TD>
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Specification <o:p></o:p></TD></TR>
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S3C6410 (ARM11) Module<o:p></o:p></TD>
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<o:p> </o:p>
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<o:p></o:p>
A. S3C6410 CPU<o:p></o:p>
B. 128MB mDDR, 1GB NAND, MicroSD Socket<o:p></o:p>
C. USB HOST 1port, OTG 1port UART 2port<o:p></o:p>
D. 229 GPIO available (2*120pin connectors)<o:p></o:p>
E. Connectors are compatible for MFP Series and RPS Series<o:p></o:p></TD></TR>
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ARM <o:p></o:p>
CT11MPCore<o:p></o:p></TD>
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Four ARM11 MPCore CPUs with VFP and 32KB L1 caches<o:p></o:p>
1MB of unified L2 cache<o:p></o:p>
2 external multiplexed AXI interfaces<o:p></o:p>
Tile form factor<o:p></o:p>
High density stacking connectors<o:p></o:p></TD></TR>
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ARM1176 Core Tile<o:p></o:p></TD>
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<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 275.4pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=367>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Single ARM1176JZF-S CPU with VFP and 16KB caches and TCMs<o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>128KB of internal AXI RAM<o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>ARM *TrustZone Technology<o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>On chip ETM11CS with external MICTOR trace connector<o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>External multiplexed 64-bit AXI interface<o:p></o:p></TD></TR>
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ARM1136 Core Tile<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 156.1pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=208><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_ad5d6952_1888497166_9dc8d3b6_4.jpg" > </TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 275.4pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=367>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>ARM1136JS-F processor test chip <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Tile form factor <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>High density stacking connectors <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Two PISMO™ connectors for memory expansion boards<o:p></o:p></TD></TR>
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ARM926 Core Tile<o:p></o:p></TD>
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<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 275.4pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=367>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>ARM926EJ-S processor test chip <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Tile form factor <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>High density stacking connectors <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Two PISMO™ connectors for memory expansion boards<o:p></o:p></TD></TR>
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ARM7 TDMI<o:p></o:p></TD>
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<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 275.4pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=367>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>ARM7TDMI processor test chip <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Tile form factor <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>High density stacking connectors <o:p></o:p>
<P style="TEXT-ALIGN: left; LINE-HEIGHT: 150%; MARGIN: 0cm 0cm 0pt; TEXT-AUTOSPACE: ideograph-numeric; WORD-BREAK: keep-all; mso-pagination: widow-orphan; tab-stops: list 36.0pt" class=MsoNormal align=left>Two PISMO™ connectors for memory expansion boards<o:p></o:p></TD></TR>
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TI DSP<o:p></o:p>
TMS320C6416 Module<o:p></o:p></TD>
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TI DSP TMS320C6416<o:p></o:p>
SDRAM included<o:p></o:p></TD></TR>
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Core Tile Adaptor<o:p></o:p></TD>
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<IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_66423623_1888497166_f9af305c_8.jpg" ></TD>
<TD style="BORDER-BOTTOM: #f4f4f4; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 275.4pt; PADDING-RIGHT: 1.5pt; HEIGHT: 16.45pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-top-alt: solid #E8E8E8 .5pt; mso-border-left-alt: solid #E8E8E8 .5pt; mso-border-right-alt: solid #E8E8E8 .5pt" width=367>
ARM Core Tile to FPGA Modules<o:p></o:p></TD></TR></TBODY></TABLE> 2.     I/O Modules for RPS-LX7601, LX7604 
</o:p><o:p></o:p>
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Item <o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #0099cc; HEIGHT: 22.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
Specification<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 1">
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DDR3 SO-DIMM <o:p></o:p>
<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_231145ed_1888497166_d6e26b32_1.jpg" > <o:p></o:p> </o:p></TD>
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DDR3 SO-DIMM for DDR3 SDRAM<o:p></o:p>
- Datawidth : 64bit<o:p></o:p>
- Staked on two 120pin connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 2">
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DDR2 SO-DIMM <o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_b2f8e8d0_B1D7B8B22.jpg" > </o:p></TD>
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DDR2 SO-DIMM for DDR2 SDRAM<o:p></o:p>
- Datawidth : 64bit<o:p></o:p>
- Stacked on two 120pin connectors<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 3">
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128MB DDR SDRAM<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_4e88c01d_1888497166_5d9d03d5_3.jpg" > </o:p></TD>
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128MB 32bit Mobile DDR SDRAM Module<o:p></o:p>
- Datawidth : 32bit<o:p></o:p>
- Stacked on one 120pin connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 4">
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64MB SDRAM<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_69d87c38_1888497166_5d9d03d5_3.jpg" > </o:p></TD>
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64MB 32bit Mobile SDR SDRAM Module<o:p></o:p>
- Datawidth : 32bit<o:p></o:p>
- Stacked on one 120pin connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 5">
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32MB NorFLASH<o:p></o:p>
<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_f265c40c_1888497166_b04417e7_5.jpg" > <o:p></o:p> </o:p></TD>
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32MB Nor Flash<o:p></o:p>
- Datawidth : 32bit<o:p></o:p>
- Stacked on one 120pin connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 6">
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UART/USB2.0<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_762fce80_1888497166_e9dc7436_6.jpg" > </o:p></TD>
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2 UART port, USB High-speed GPIF(CY7C68013A)<o:p></o:p>
- Stacked on one 120pin connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 7">
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Gigabit Ethernet Phy<o:p></o:p>
<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_762fce80_1888497166_e9dc7436_6.jpg" > </o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
Gigabit Ethernet Phy(M88E111)<o:p></o:p>
- Staked on two 120pin connector<o:p></o:p>
- Form factor : 1x1 (occupies one daughter board connector)<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 8">
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PCI Express Phy<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_86f0d508_1888497166_90554f02_7.jpg" > </o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
<o:p> </o:p>
PCI Express Phy 1Lane(PX1011)<o:p></o:p>
- Stacked on one 120pin connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 9">
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DVI <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_0717652a_1888497166_a3bfcee8_8.jpg" > <o:p></o:p></TD>
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Rx : SIL-1161<o:p></o:p>
ㆍsupport high-resolution displays up to UXGA (25-165MHz).<o:p></o:p>
ㆍsupports up to true color panels (24 bits per pixel, 16M colors) with both one and two pixels per clock.<o:p></o:p>
Tx : SiL-1160<o:p></o:p>
ㆍsupport displays up to UXGA resolution.<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 10">
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TFT LCD Module<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_6fca0e7d_1888497166_5324a1ce_9.jpg" > </o:p></TD>
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4.3” TFT LCD Interface(24-bit Color)<o:p></o:p>
5” WVGA (800x480) TFT LCD (24-bit Color)<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 11">
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HDMI<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
<o:p> </o:p>
<o:p> </o:p>
<o:p> </o:p></TD></TR>
<TR style="mso-yfti-irow: 12">
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ADC/DAC <o:p></o:p>
<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_0e787b33_1888497166_18d7727e_1.jpg" > <o:p></o:p> </o:p>
<o:p> </o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
ADC : 2channel 125Msps<o:p></o:p>
ㆍ14bit 125Msps ㆍHigh SNR : 70.5dBFS at 100MHz fIN<o:p></o:p>
ㆍ2.3VPP Differential Input Voltage ㆍHigh SFDR : 82dBFS at 100MHz fIN<o:p></o:p>
ㆍInternal Voltage Reference ㆍ3.3V Single-Supply Voltage<o:p></o:p>
ㆍAnalog Power Dissipation : 578mW ㆍTotal Power Dissipation : 780mW<o:p></o:p>
DAC : 2channel 165Msps<o:p></o:p>
ㆍ14bit 125Msps ㆍSINGLE + 5V OR +3V OPERATION<o:p></o:p>
ㆍHIGH SFDR : 20MHz Output at 100MSPS : 64dBc<o:p></o:p>
ㆍLOW GLITCH : 3pV-s ㆍLOW POWER : 170mW at +5V<o:p></o:p>
ㆍINTERNAL REFERENCE : Optional Ext. Reference, Adjustable Full-Scale<o:p></o:p>
Range, Multiplying Optionv<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 13">
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PROBE HEADER </TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
HEADER CONNECTORs for Probing<o:p></o:p>
- Stacked on one 120pin connector<o:p></o:p>
- 40 header * 4<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 14">
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PROBE MICTOR<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_16bb301f_1888497166_927995c9_2.jpg" > </o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
MICTOR CONNECTORs for Probing<o:p></o:p>
- Stacked on one 120pin connector <SPAN style="FONT-FAMILY: 굴림; COLOR: black; FONT-SIZE: 10pt; mso-bidi-font-family: 굴림; mso-font-kerning: 0pt; mso-ansi-language: EN-US; mso-fareast-language: KO; mso-bidi-language: AR-SA; mso-themecolor: text1" lang=EN-US>- MICTOR Connector * 4</TD></TR>
<TR style="mso-yfti-irow: 15">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 163pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=217>
Interconnect CON 1X1<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_40998393_1888497166_16de1c7f_3.jpg" ></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
1 connector for stackable height<o:p></o:p>
ㆍForm factor : 1x1 (occupies one daughter board connector)<o:p></o:p>
ㆍConnects GND in the two connectors<o:p></o:p>
ㆍVCCO (B60) can be disconnected<o:p></o:p>
ㆍThe dedicated clock pin (A60) can be cross connected to A59<o:p></o:p>
ㆍConnects the remaining 117 signals in the connectors directly<o:p></o:p>
ㆍAvailable in 2 different heights<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 16">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 163pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=217>
Interconnect CON 2X1<o:p></o:p>
<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_a5f0fde4_1888497166_0a580e3d_4.jpg" > <o:p></o:p> </o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
2 interconnect for 2 horizontal connectors<o:p></o:p>
ㆍForm factor : 2x1 (occupies two daughter board connectors)<o:p></o:p>
ㆍConnects 117 signals between two connectors. The signals can be individually disconnected.<o:p></o:p>
ㆍConnects the dedicated clock pins, A60, either straight or crossed to A59<o:p></o:p>
ㆍConnects GND in the two connectors<o:p></o:p>
ㆍVCCO (B60) in the two connectors can be connected together<o:p></o:p>
ㆍ“Top side” connectors allows other daughter boards to share the bus with the FPGAs<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 17; mso-yfti-lastrow: yes">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 163pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=217>
Interconnect CON 1X2<o:p></o:p>
<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1004/3536717426_a5f0fde4_1888497166_0a580e3d_4.jpg" ></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 320.95pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=428>
2 interconnect for 2 vertical connectors<o:p></o:p></TD></TR></TBODY></TABLE>

<IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' style="VERTICAL-ALIGN: middle; CURSOR: pointer" onclick=image_window(this) name=target_resize_image[] src="http://huins2.designpixel.or.kr/_data/_editor/1003/2040968486_161da8fd_square_arrow.gif" tmp_width="14" tmp_height="16" > 제품 구성도 1.     DVI 모듈 (1)   사양 <SPAN style="mso-bidi-font-family: '맑은 고딕'; mso-font-kerning: 0pt; mso-bidi-font-size: 10.0pt; mso-fareast-font-family: '맑은 고딕'; mso-fareast-theme-font: major-latin; mso-ascii-font-family: '맑은 고딕'; mso-hansi-font-family: '맑은 고딕'; mso-ascii-theme-font: major-latin; mso-hansi-theme-font: major-latin; mso-bidi-theme-font: major-latin" lang=EN-US><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_b9cfd42b_1.jpg" > 
A. Transmitter IC : Sil1160<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p>
- Bandwidth : 25-165MHz(VGA to UXGA)<o:p></o:p>
B. Receiver IC : Sil1161<o:p></o:p>
- Bandwidth : 25-165MHz(VGA to UXGA)<o:p></o:p>
C. DVI 1.0 Compliant 
(2)제공예제<o:p></o:p>
A. Receiver to Transmitter Test<o:p></o:p>
 i. RX 포트에 이미지소스(PC등)을 연결하고<o:p></o:p>
ii. TX 포트에 디스플레이(모니터)를 연결하여 DVI RX/TX의 Path Test<o:p></o:p>
<SPAN style="mso-bidi-font-family: 굴림; mso-font-kerning: 0pt; mso-bidi-font-size: 10.0pt; mso-fareast-font-family: '맑은 고딕'; mso-fareast-theme-font: major-latin; mso-ascii-font-family: '맑은 고딕'; mso-hansi-font-family: '맑은 고딕'; mso-ascii-theme-font: major-latin; mso-hansi-theme-font: major-latin" lang=EN-US><o:p> </o:p><o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_184c8f49_1.jpg" > </o:p><SPAN style="mso-bidi-font-family: '맑은 고딕'; mso-font-kerning: 0pt; mso-bidi-font-size: 10.0pt; mso-fareast-font-family: '맑은 고딕'; mso-fareast-theme-font: major-latin; mso-ascii-font-family: '맑은 고딕'; mso-hansi-font-family: '맑은 고딕'; mso-ascii-theme-font: major-latin; mso-hansi-theme-font: major-latin; mso-bidi-theme-font: major-latin" lang=EN-US> 
B. ColorBar output(Transmitter use only)<o:p></o:p>
i. TX 포트에 디스플레이를 연결하여 ColorBar를 출력하여 DVI RX Test 2.     CIS모듈 (1)   사양 <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_d89dbe58_1.jpg" > 
B. ColorBar output(Transmitter use only)<o:p></o:p>
i. TX 포트에 디스플레이를 연결하여 ColorBar를 출력하여 DVI RX Test<o:p></o:p>
A. SiliconFile NOON200PC11 사용<o:p></o:p>
B. 2Mega(1/3”) CMOS Image Sensor with Image Signal Processor<o:p></o:p>
C. Output Format<o:p></o:p>
- YUV4:2:2, RGB5:6:6, RGB6:6:6, ITU656-like 
(2) 제공예제<o:p></o:p>
A. CIS-to-TFTLCD<o:p></o:p>
i. CIS 모듈 소켓에 CIS모듈을 연결하여, 영상을 TFT-LCD에 출력<o:p></o:p>
 3. S3C6410모듈<o:p></o:p>
<o:p></o:p>
<o:p> </o:p>

<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_4aa893d6_2.jpg" > </o:p><o:p> 
1. 사양<o:p></o:p>
A. S3C6410 CPU<o:p></o:p>
B. 128MB mDDR, 1GB NAND, MicroSD Socket<o:p></o:p>
C. USB HOST 1port, OTG 1port UART 2port, <o:p></o:p>
D. 229GPIO available (2 120pin connectors)<o:p></o:p>
E. MFP Series and RPS Series Connector compatible<o:p></o:p>
 </o:p>
<o:p>  </o:p>4. TI DSP모듈 1.     사양 
- TI TMS320C6416 DSP/1GHz - 1MB NOR FLASH / 64MB SDRAM - EMIFA/B 사용<o:p></o:p>
 2.     예제 
A. DPRAM Interface B. EMIFA를 통한 FPGA DPRAM 연결 및 메모리 테스트 C. FPGA RTL및 메모리테스트S/W D. DSP개발환경 : CCS3.1<o:p></o:p>
<o:p> </o:p>
 5.     DDR/DDR2/DDR3 메모리 모듈 (1)   DDR3<o:p> </o:p><o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_b8cc3382_3.jpg" > <o:p></o:p>  <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_d0d25e1e_4.jpg" > </o:p> (2)   DDR2<o:p> <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_cce24494_9.jpg" > <o:p></o:p>  </o:p>6.     고속 통신 인터페이스 회로 설계 <IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_16cc0c41_1.jpg" > l  PCIe, PCI, ExpressCard, USB3.0, USB2.0, Gigabit Ethernet, 10G Ethernet 7.     DISPLAY Interface l  DVI T/R, HDMI T/R, CAM-LINK, TFT-LCD 8.     AUDIO Interface l  AC97, I2S, SPDIF
<o:p> </o:p>

<MFP Module Display>
<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_5afd9ff4_2.jpg" > <o:p></o:p> </o:p>
 9.     Signal Procesing l  High-Speed ADC/DAC
<o:p> </o:p>

<o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' src="/_data/_editor/1003/1888497166_618fa059_3.jpg" > <o:p></o:p> </o:p>

<?xml:namespace prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p><IMG name='target_resize_image[]' onclick='image_window(this)' style='cursor:pointer;' style="VERTICAL-ALIGN: middle; CURSOR: pointer" onclick=image_window(this) name=target_resize_image[] src="http://huins2.designpixel.or.kr/_data/_editor/1003/2040968486_161da8fd_square_arrow.gif" tmp_width="14" tmp_height="16" > 제품 사양  </o:p>
<DIV align=center>
<TABLE style="MARGIN: auto auto auto 16.1pt; WIDTH: 442.4pt; mso-yfti-tbllook: 1184; mso-padding-alt: 1.5pt 1.5pt 1.5pt 1.5pt; mso-cellspacing: 0cm" class=MsoNormalTable border=1 cellSpacing=0 cellPadding=0 width=590>
<TBODY>
<TR style="HEIGHT: 22.5pt; mso-yfti-irow: 0; mso-yfti-firstrow: yes">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #006699; HEIGHT: 22.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
Item <o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #0099cc; HEIGHT: 22.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
Specification <o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 1">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
CON 1X1<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
1 connector for stackable height<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 2">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
CON 2X1<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
2 interconnect for 2 horizontal connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 3">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
CON 1X2<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
2 interconnect for 2 vertical connector<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 4">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
PROBE HEADER<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
HEADER CONNECTORs for Probing<o:p></o:p>
-      1 Connector use<o:p></o:p>
-      40 header * 4<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 5">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
PROBE MICTOR<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
MICTOR CONNECTORs for Probing<o:p></o:p>
-      1Connector use<o:p></o:p>
-      MICTOR Connector * 4<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 6">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
32MB NorFLASH<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
32MB Nor Flash<o:p></o:p>
<A name=OLE_LINK3>-      Datawidth : 32bit<o:p></o:p></A>
-      1 connector use<o:p></o:p></TD></TR>
<TR style="HEIGHT: 16.45pt; mso-yfti-irow: 7">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; HEIGHT: 16.45pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
64MB SDRAM<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #ece9d8; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; HEIGHT: 16.45pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-top-alt: solid #E8E8E8 .5pt; mso-border-left-alt: solid #E8E8E8 .5pt; mso-border-right-alt: solid #E8E8E8 .5pt" width=419>
64MB 32bit Mobile SDR SDRAM Module<o:p></o:p>
-      Datawidth : 32bit<o:p></o:p>
-      1 connector use<o:p></o:p></TD></TR>
<TR style="mso-yfti-irow: 8">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
128MB DDR SDRAM<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
128MB 32bit Mobile DDR SDRAM Module<o:p></o:p>
-      Datawidth : 32bit<o:p></o:p>
-      1 connector use<o:p></o:p></TD></TR>
<TR style="HEIGHT: 10.1pt; mso-yfti-irow: 9">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
DDR2 SO-DIMM <o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
DDR2 SO-DIMM for DDR2 SDRAM<o:p></o:p>
-      Datawidth : 64bit<o:p></o:p>
-      2 connectors use<o:p></o:p></TD></TR>
<TR style="HEIGHT: 10.1pt; mso-yfti-irow: 10">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
DDR3 SO-DIMM <o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
DDR3 SO-DIMM for DDR3 SDRAM<o:p></o:p>
-      Datawidth : 64bit<o:p></o:p>
-      2 connectors use<o:p></o:p></TD></TR>
<TR style="HEIGHT: 10.1pt; mso-yfti-irow: 11">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
UART/USB2.0<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
2 UART port, USB High-speed GPIF(CY7C68013A)<o:p></o:p>
-      1 connector use<o:p></o:p></TD></TR>
<TR style="HEIGHT: 10.1pt; mso-yfti-irow: 12">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
Gigabit Ethernet Phy<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=419>
Gigabit Ethernet Phy(M88E111)<o:p></o:p>
-      1 connector use<o:p></o:p></TD></TR>
<TR style="HEIGHT: 10.1pt; mso-yfti-irow: 13; mso-yfti-lastrow: yes">
<TD style="BORDER-BOTTOM: #e8e8e8 1pt solid; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; PADDING-LEFT: 1.5pt; WIDTH: 128.5pt; PADDING-RIGHT: 1.5pt; BACKGROUND: #e8f3ff; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-alt: solid #E8E8E8 .5pt" width=171>
PCI Express Phy<o:p></o:p></TD>
<TD style="BORDER-BOTTOM: #ece9d8; BORDER-LEFT: #e8e8e8 1pt solid; PADDING-BOTTOM: 1.5pt; BACKGROUND-COLOR: transparent; PADDING-LEFT: 1.5pt; WIDTH: 313.9pt; PADDING-RIGHT: 1.5pt; HEIGHT: 10.1pt; BORDER-TOP: #e8e8e8 1pt solid; BORDER-RIGHT: #e8e8e8 1pt solid; PADDING-TOP: 1.5pt; mso-border-top-alt: solid #E8E8E8 .5pt; mso-border-left-alt: solid #E8E8E8 .5pt; mso-border-right-alt: solid #E8E8E8 .5pt" width=419>
PCI Express Phy 1Lane(PX1011)<o:p></o:p>
-      1 connector use<o:p></o:p></TD></TR></TBODY></TABLE></DIV>
<o:p> </o:p>