SoC/ASIC Design and Verification System based on 4 Virtex-6 LX760

 ASIC 28M~56M Gates

 Supports ARM Cortex A9, A8, ARM11, ARM926, ARM1176, MPCore

 Trace Length Matching for each pins of FPGA

 Minimize Clock Skew with Clock Generator/Buffer

 High Speed LVDS, Impedance Matching

 Level Shifter Board for 2.5V daughter boards

 Total 3134 I/O pins available

 Separate power design for each connectors

 Includes DDR3 Memory Controller (Xilinx MIG), SystemACE

 Peripherals :DDR3, Core Tile Adaptors, AD/DA, SDRAM module, SRAM, Flash