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RPS-7604
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SoC/ASIC Prototyping system with 4~8 Virtex-6 LX760 FPGA FPGA Gates : 280M Gates~ 500M Gates,
ASIC Gate: 28M Gates ~ 50M Gates 8 RPS-760M Logic Tile can be stacked Interface Adaptor for ARM Cortex A8, ARM11 (S3C6410),
ARM926, ARM136 Trace Length Matching for minimizing skew LVDS Impedance matching for LVDS operation Support DDR2/DDR3 SDRAM by XilinX MIG Supports peripherals Clock Generator and Fan-out Buffer JTAG and SelectMAP Configuration SystemACE Configuration
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