SoC/ASIC Prototyping system with 1~4 Virtex-6 LX760 FPGA
 FPGA Gates : 70M Gates~ 210M Gates,
  ASIC Gate: 7M Gates ~ 20M Gates
 8 RPS-760M Logic Tile can be stacked
 Interface Adaptor for ARM Cortex A8, ARM11 (S3C6410),
  ARM926, ARM136
 Trace Length Matching for minimizing skew
 LVDS Impedance matching for LVDS operation
 Support DDR2/DDR3 SDRAM by XilinX MIG
 Supports peripherals
 Clock Generator and Fan-out Buffer
 JTAG and SelectMAP Configuration
 SystemACE Configuration