ARM Cortex-R4F test chip

 512MB (64M x 64) of local SDRAM memory

 clock selection and initialization logic

 configuration and control PLD
 4-wire serial interface

 ARM Cortex-R4F test chip signal routing

 bus interface logic

 bottom tile headers for connection to
 a baseboard or Logic Tile

 DVI video interface with analog VGA support.

 Configuration switches and status LEDs

 power supplies for the test chip core,
 and PLLCT-R4F PLD core