ARM
Achro
¾Èµå·ÎÀ̵å
SoC
RVDS
FPGA
Compiler
KEIL
Cortex
USN
LX760
HOME
±â¼úÁö¿ø
SoC¼Ö·ç¼Ç Q&A 8 ÆäÀÌÁö
59
vip-1000 ¸Þ´º¾óÁ» ºÎŹµå¸³´Ï´Ù.
Á¤ÀÏÁ¾
02-20
170
58
[re]vip-1000 ¸Þ´º¾óÁ» ºÎŹµå¸³´Ï´Ù.
SoCÆÀ
03-24
167
57
CIS_tftLCD ¿¹Á¦¿¡¼ ,,
¼³±â¼ö
02-12
185
56
[re]CIS_tftLCD ¿¹Á¦¿¡¼ ,,
SoCÆÀ
02-12
195
55
·¥µð½ºÅ© Å©±â º¯°æ
Á¤´ö±â
12-07
114
54
TFT LCD Module [3.5\' COLOR TFT_LCD MV 2.0 ] datasheet ¹®ÀÇ
±è¼¼È£
12-04
118
53
·¥µð½ºÅ© È®Àå
±èÈÁØ
12-03
101
52
Timer¸¦ ÀÌ¿ëÇÏ¿© 5ms IRQ ¸¦ ¸¸µé±â
¹Ú¼ºÈ
10-31
104
51
VIP-1000°ü·Ã ¹®ÀÇ µå¸³´Ï´Ù.
¿Á½ÂÈ£
10-25
138
50
[re]VIP-1000°ü·Ã ¹®ÀÇ µå¸³´Ï´Ù.
SoCÆÀ
10-29
130
49
socmaster3¿¡¼ SW¸¦ ÅëÇØ sramÀ» »ç¿ëÇÏ°í ½Í½À´Ï´Ù.
À±¼ºÁø
10-22
127
48
CIS-TFT_LCD °ü·Ã Verilog ¿¹Á¦ ÆÄÀÏÀº ¾ø³ª¿ä?
¼ÛÁøö
10-19
132
47
VIP1000¿¡¼ DSP »ç¿ë½Ã ±Ã±ÝÁ¡.
¾ö±âÈ£
09-19
102
46
CIS-TFTLCD EXAMPLE[VERILOG-SRC]¿¡ ´ëÇØ Áú¹®
ÁÖÇö¿õ
06-30
80
45
Image Conversion (BMP->hex) ¿¡·¯ ¹ß»ý
±è¿ìÁß
06-03
48
1
2
3
4
5
6
7
8
9
10
Á¦¸ñ
³»¿ë
Á¦¸ñ+³»¿ë
and
or